1. Field of the Invention
The present invention relates to a semiconductor integrated circuit having a static memory (SRAM) circuit integrated on a semiconductor chip. More specifically, it relates to constitution for reducing the operating voltage of a SRAM integrated circuit device.
2. Description of Related Art
JP-A 139779/1994 discloses a circuit for comparing the threshold voltage of the transistor of a memory cell with a preset reference voltage and generating a substrate bias voltage so that the threshold voltage becomes equal to the reference voltage. JP-A 268574/2000 discloses a circuit for changing a substrate bias voltage using signals from a threshold value detection circuit and from a voltage detection circuit for transistors to approximate the threshold value of the transistor of a memory cell to a preset value.
The operating voltages of large scale integrated circuits (LSIs) are decreasing due to reductions in the power consumption of LSIs and the process pattern rule of transistors in the LSIs. For example, an LSI which operates at a operating voltage of 1.2 V is produced at a process pattern rule of 0.13 μm. To reduce the operating voltage of the LSI, the current of a transistor is increased by reducing the threshold voltage of the transistor in order to prevent deterioration in circuit performance (working speed of a circuit). When the threshold voltage of the transistor is reduced, the static noise margin (SNM) which is the operation margin for reading the data of a SRAM memory cell becomes small, thereby making it difficult to operate the circuit. When the operating voltage is further reduced, the operation margin for not only reading but also writing becomes smaller with the result that the SRAM circuit does not operate. Therefore, the operation margin for reading and writing data from and to the SRAM memory cell must be made large even at a low operating voltage.